In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs), which are fabricated using conventional lithographic fabrication methods, non-planar FETs incorporate various vertical transistor structures. One such transistor structure is the FinFET, which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width. For example, FIG. 1 illustrates a simplified perspective view of a FinFET 100, which is formed on a semiconductor silicon substrate 102 and a dielectric material such as silicon dioxide (SiO2) 104. The silicon substrate 102 includes a rectangular shaped fin 106, which extends from a source region 108, through a channel region 110, to a drain region 112. These regions are formed of one or more n-type or p-type doped semiconductor materials. As shown, channel region 110 is surrounded on the top and on each side by a gate electrode 114. The combined top and side surface areas of the channel region 110 determine the effective channel of the FinFET 100. The gate electrode 114 is isolated from the fin 106 via a gate oxide (not shown for illustrative convenience). When switched on, the gate electrode 114 provides a path (conducting channel) for current to flow from the source region 108 to the drain region 112.
One of the goals of the semiconductor industry is to increase the on current of individual FinFETs while decreasing their size. For transistors, the on current is given by equation I:
                                          I                          o              ⁢                                                          ⁢              n                                ≈                      μ            ⁢                                                  ⁢                          C                              o                ⁢                                                                  ⁢                x                                      ⁢                                          W                                  s                  ⁢                                                                          ⁢                  i                                                            L                g                                      ⁢                                          (                                                      V                                          d                      ⁢                                                                                          ⁢                      d                                                        -                                      V                                          t                      ⁢                                                                                          ⁢                      h                                                                      )                            2                                      ,                            (        I        )            where Wsi is the width of the device, i.e. the width of the area underneath the gate, Lg is the gate length, Vdd is the supply voltage, μ is the carrier mobility and Cox is the gate oxide capacitance. A known approach for increasing the on current is to increase the width of the device under the gate. To put more transistors into a FinFET without increasing its surface area, many structures have been developed that increase the width of the device in the vertical direction, e.g. double-gate, triple-gate, quadruple-gate, cylindrical-gate, independent-gate/extremely thin silicon-on-insulator (ETSOI), and bulk FinFET devices. However, structures that increase the width in the vertical direction, (e.g. double-gate, triple-gate, quadruple-gate, cylindrical-gate, independent-gate/ETSOI, and bulk FinFET devices) require growing a uniform nanowire, which includes expensive and complicated integration steps. Further modifications of these structures, accordingly, are needed to meet the increasing goals of the industry.
A need therefore exists for methodology enabling the increase of on current of a FinFET without increasing its size, and the resulting device.